Layout

•  Describes actual layers and geometry on the silicon substrate to implement a function
•  Need to define transistors, interconnection 
• Transistor widths (for performance)
•  Spacing, interconnect widths, to reduce defects, satisfy power requirements 
• Contacts (between poly or active and metal), and vias (between metal layers)
•  Wells and their contacts (to power or ground) 
• Layout of lower-level cells constrained by higher-level requirements:  floorplanning

CMOS Inverter Layout