VLSI TESTING

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Spice Circuit Simulator

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Formal Verification

Basic Terminology

Mostly Used Formal Methods:

1. Equivalence Checking
2. Model Checking
3. Theorem  Provoking.

•  Theorem Proving: Relationship between a specification and an implementation is regarded as a theorem in a logic, to be proved within the framework of a proof calculus 
• Used for verifying arithmetic circuits in industry
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• Model Checking: The specification is in the form of a logic formula, the truth of which is determined with respect to a semantic model provided by an implementation Starting to be used to check small modules in industry 
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• Equivalence Checking: The equivalence of a specification and an implementation checked Most common industry use of formal verification
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•  Symbolic Trajectory Evaluation: Properties specified as assertions about circuit state (pre- and post- conditions), verified using symbolic simulation 
• Used to verify embedded memories in industry

 

Low Power Reduction Techniques

 

Possible Future Transistors in VLSI

 

As the cost and complexity of each new process node has continued rising, advances have slowed noticeably, despite the fact that there are applications such as AI and machine learning, big data analysis and data center servers that require the latest and most powerful CMOS solutions.

Why? It has become so much more difficult to use MOSFET scaling techniques to achieve continued miniaturization that perpetuating Moore’s Law may finally pose manufacturing and fab-cost challenges that cannot be met.

Since its introduction in 1959, the field-effect transistor (FET) has been mostly built in the plane of the silicon. In 2012, at 20nm, the industry made the first transition from “planar” MOSFETs to fin field-effect transistor (FinFET) architectures to maintain the Moore’s Law scaling path.

In a FinFET, the channel between source and drain terminals is in the form of a fin. As compared to planar transistors, the fin – contacted on three sides by the gate – provided better control of the channel formed within the fin. As a result, FinFETs helped significantly with current leakage. Since then, fin height has been increased to obtain a higher device drive current at the same footprint. Today's designs place the gate stack directly above the channel area.

Drawback of Finfet:

One problem is that as these structures become smaller, it becomes more difficult to block the charge leak across the transistor. With FinFETs, the gate surrounds the rectangular silicon fin on three sides, leaving the bottom side connected to the body of the silicon. This allows some leakage current to flow when the transistor is off. The resulting leakage leads to hotter, less power-efficient microchips

Nanosheet/Gate all Around Transistors Or nanowire Transistors Vs   FINFET:

1. Unlike FinFET technology, in nanosheet technology the gate surrounds the channel region in its entirety, providing even better control of current leakage. This stacked structure supports far more advanced semiconductor fabrication processes, including a channel region that is tilted upward to create a wider path for current.
2. Rather than the transistor consisting of a vertical fin of silicon, the nanosheet’s channel region consists of multiple, horizontal, nanometer-thin sheets stacked atop one another. Nanosheet FETs incorporate several components, including a channel, which allows electrons to flow through the transistor.
3.  Nanosheets offer excellent electrostatics and short channel control, and can be fabricated with minimal deviation from FinFET.
4. A narrow nanosheet has less drive current, but takes up a smaller area. The narrow nanosheet also requires a more complicated, costly manufacturing process.

Integrated Circuit(IC) Package Types

 

Package Types

Layout

•  Describes actual layers and geometry on the silicon substrate to implement a function
•  Need to define transistors, interconnection 
• Transistor widths (for performance)
•  Spacing, interconnect widths, to reduce defects, satisfy power requirements 
• Contacts (between poly or active and metal), and vias (between metal layers)
•  Wells and their contacts (to power or ground) 
• Layout of lower-level cells constrained by higher-level requirements:  floorplanning

CMOS Inverter Layout

Complementary Switch (Transmission Gate)

 Combine n- and p-channel switches in parallel to get a switch which passes both ‘1’ and ‘0’ well.

Multiplexer Using Transmission Gate:

PMOS AND NMOS

 » A pMOS is a device that generates “Strong Ones”. 

» An nMOS is a device that generates “Strong Zeros”.

Schmitt Trigger_ CMOS Implementation

VLSI Transistor Fabrication Steps/ MOSFET Operation

 VLSI Transistor Fabrication Steps:

MOSFET Structure

Mathematical Model of  MOSFET

SRAM VS DRAM

 Static( SRAM) 

• Data is Stored as long as supply is applied.
• Larger (6 Transistors/Cell).
• Very Fast
• Differential (Usually)

Dynamic(DRAM)

• Periodic Refresh Required
•  Smaller (1-3 Transistors/Cell)
• Slower 
•  Single Ended

6 Transistor CMOS SRAM CELL

1 Transistor DRAM Cell

3 Transistor DRAM Cell

DYNAMIC METRICS

 Propagation Delay (tp , tpd, tdelay) defines how quickly a gate responds to a change in its inputs.

•  It expresses the delay experienced by a signal when passing through a gate
• tpd is measured between the 50% transition points of the input and output waveforms.

Rise Time (tr ) is the time it takes a signal to rise from 10% to 90% of its full level. 

 Fall Time (tf ) is the time it takes a signal to fall from 90% to 10% of its full level. 

Histrory of Digital Integrated Circuits- The Transistor Era

 

What is LOGIC EFFORT???

• Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current
•     Measure from delay vs. fanout plots Or, estimate by counting transistor widths
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